This relates generally to imaging systems, and more particularly to clocking methods for interline charge coupled device (CCD) image sensors that reduce lag, improve smear, reliability, and dark current performance, enable the use of low clocking voltages, and enable faster readout of image sensors.
Electronic devices such as cellular telephones, cameras, and computers often include imaging systems that include digital image sensors for capturing images. Image sensors may be formed having a two-dimensional array of image pixels that contain photodiodes that convert incident photons (light) into electrical signals. Electronic devices often include displays for displaying captured image data.
Conventional interline CCD imagers are provided with multiple photodiodes that are formed below a pinning layer. In a conventional imager, the photodiodes are typically n-type doped regions in a semiconductor substrate. The pinning layer formed over the photodiodes is usually a p-type doped layer. The pinning layer formed over the photodiodes is conventionally coupled to ground and serves as a ground for the photodiode. The potential of the photodiode remains constant as long as the voltage provided at the pinning layer is constant, and there is no net global current flow throughout the device.
Light incident on the imager results in the accumulation of photo-generated electrons in the n-type photodiode region. Some of these photo-generated electrons are read out into a vertical CCD (VCCD) by applying a read-out voltage (sometimes referred to as the “third-level voltage”) to a transfer gate that is formed over the VCCD and a region between the photodiode and the VCCD.
The “third-level voltage” conventionally used in the readout of photo-generated charges from photodiodes to the VCCD is usually a large voltage such as 12V. The large voltage applied to the transfer gate that is formed over the VCCD causes holes, which are the majority charge carrier in the p-type pinning layer formed over the photodiodes, to be repelled. The global current generated by the movement of holes in the pinning layer formed over the photodiodes results in a voltage drop (sometimes referred to as an “I-R drop”) of the voltage in the pinning layer. The inconstancy of the voltage at the pinning layer is referred to as “well bounce,” and can be detrimental to the performance of an imager.
Well bounce increases the readout time of a photodiode because the global currents must be allowed time to settle, thereby limiting the speed and efficiency of an imager. Because the potential of the photodiode is no longer “pinned” by a constant ground voltage at the pinning layer formed over the photodiode, the step in voltage potential between photodiode and the VCCD is reduced. In instances where the pinning layer voltage varies substantially, the decrease in the voltage potential step between the photodiode and the VCCD makes it impossible to completely transfer all of the photo-generated charge out of the photodiode into the VCCD.
The inconstancy of the pinning layer voltage level spatially varies across a conventional imager. As an example, a first pinning region associated with a first photodiode at an edge of the imager may be close to a ground supply voltage that provides the ground voltage to the first pinning region. Therefore, when the photodiode is read out, the current generated by the movement of holes in the pinning layer in which the first pinning region is located does not result in a large voltage drop, because the distance to the ground supply is small. However, a second pinning region associated with a second photodiode at the center of the imager may be separated from the ground supply that provides the ground voltage to the second pinning region by a greater distance. As a result, when the photodiode is read out, the current generated by the movement of holes in the pinning layer in which the second pinning region is located will result in a large voltage drop (or, a large “well bounce”).
Because well bounce varies as a function of the location of a photodiode on the imager, the inconsistencies in the photodiode readout may result in visible image artifacts, or a fixed pattern artifact in the image data.
A number of techniques have been developed in an attempt to alleviate the well bounce problem. One technique involves the addition of well contacts within the pixel array, as described in, for example, U.S. Pat. No. 7,016,089, entitled “Amplification-Type Solid State Imaging Device with Reduced Shading.” Unfortunately, this addition of well contacts within the pixel array takes up limited die area that could otherwise be used for sensing light, and thus adversely impacts the performance of the image sensor. Also, ground contacts to silicon are known to generate bright points because the contact is not positively biased and thus does not drain off charge generated by defects created at the contact/semiconductor interface. Another technique involves reducing the clock speed for certain signals associated with sampling and readout of the pixels. See, for example, U.S. Patent Application Publication No. 2005/0001915, entitled “Solid-State Imaging Device and Drive Control Method for the Same.” However, slower clocking means it will take longer to read out the pixel data associated with a given image.
Once the photo-generated charge is transferred to the VCCD, dark current signal adds to the photo-generated charge packet, corrupting the signal. Dark current signal is influenced by temperature, metallic impurity concentration, density of unpassivated silicon bonds (surface states), readout-time, line-time, and whether the VCCD timing is operated in “depletion mode” or “accumulation mode.”
For “depletion mode” timing, one or more VCCD gates are biased at the mid-level voltage and one or more VCCD gates are biased at the low-level voltage during line readout. For “accumulation mode” clocking, all VCCD gates are biased at the low-level voltage during line readout. Dark current generation is much lower for gates held at the more negative low-level voltage because the low-level voltage is typically biased just past the threshold for accumulating holes at the silicon-dielectric interface. Holes accumulated at the surfaces “quench” the dark current generated by unpassivated silicon bonds.
Dark current for “depletion mode” timing is typically 2 or more orders of magnitude greater than for “accumulation mode” timing, thus “accumulation mode” timing is the preferred timing for reduced dark current performance. However just like “third-level” readout, well bounce complicates reading out the VCCD in “accumulation mode”. Well bounce is typically not an issue for “depletion mode” timing because clock edges are compensated. Here compensated means that for every gate that transitions from a low-level voltage to a mid-level voltage there is an adjacent gate that transitions from a mid-level voltage to a low-level voltage. Therefore if the gate capacitances are properly matched there is only a local flow of holes between adjacent gates, and no global flow of holes resulting in well bounce.
It is possible to reduce or eliminate well bounce for “accumulation mode” timing by applying a voltage more negative than the low-level voltage. The compensating voltage applied to another gate adjacent to the given gate is usually a negative voltage with a large magnitude, such as −11 V. The problem with the −11V compensation pulse is reliability.
The low-level voltage is almost always specified such that the regions of the VCCD that underlie the gate contacts on which the low-level voltage is applied are biased just past the threshold for accumulating holes at the silicon-dielectric interface. This state is a compromised state that balances dark current performance with reliability. Reliability issues occur when clocking gates back and forth between depletion (such as when the mid-level voltage is applied) and accumulation (such as when the low-level or compensating voltage is applied), causing the flow of holes along the surface. Occasionally a hole has enough energy to disrupt a hydrogen-silicon (H—Si) bond at a passivate interface state, dislodging the hydrogen from the surface.
If the gate is negative, such as when the low-level voltage is applied to the gate, the hydrogen drifts away from the Si/dielectric interface since atomic H is positively charged. These events increase the number of unpassivated interface states, and therefore increase the VCCD dark current. This mechanism is identical to the better-known Negative Bias Temperature Instability (NBTI) for CMOS parts, as reviewed by D. K. Schroder and J. A. Babcock in “Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing”. The more negative the voltage the more severe the reliability problem. Thus for reliability purpose, the low-level voltage is often specified just low enough to accumulate the surface with holes. This voltage is sufficient to significantly reduce VCCD dark current, but not too low as to increase the accumulated hole density, and hence the probability of a NBTI event.
In conventional imagers, the −11V compensation voltage pulse accumulates a high density of holes. The accumulation and flow of these excess holes dramatically increases the likelihood of NBTI degradation. Since clocking the imager by providing a compensating voltage pulse on a gate formed on the VCCD (sometimes referred to as “accumulation mode clocking”) provides lower dark current, and clocking the imager without providing the compensating voltage pulse on a VCCD gate (sometimes referred to as “depletion mode clocking”) provides larger VCCD capacity, many camera designers like to have the option of either timing depending on light condition. However, accumulation mode clocking is incompatible with depletion mode clocking because of the accelerated NBTI that results from conventional accumulation mode clocking. Also, for cameras that only use accumulation mode clocking, the NBTI degradation can be so extreme as to increase the VCCD dark current to unacceptable levels.
Accordingly, what is needed is a technique that significantly reduces or eliminates well bounce for “third-level” timing, “accumulation mode” timing, and other timings with uncompensated clock edges and while avoiding the disadvantages associated with the above-noted conventional techniques.